Pro AV Catalog
 
Request Quote
All Products

500/600MHz TigerSHARC Processor with 24MB On-chip Embedded DRAM

Model: ADSP-TS201S

  • Static superscalar architecture which supports 1-, 8-, 16- and 32-bit fixed point as well as floating point data processing
  • High performance up to 600MHz, 1.67ns instruction rate DSP core
  • 24MB on-chip embedded DRAM internally organized in six banks with user-defined partitioning
  • Enhanced communications instruction set for wireless infrastructure applications allows for TigerSHARC processor to offer complete baseband processing
  • 14 channel, zero overhead DMA controller
Compare
Project List
Product Info
Tech Specs
Documents
ADSP-TS201S is one of members of TigerSHARC processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI's TigerSHARC processor is well-suited to video and communication markets, including 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS201S features static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with leading edge multiprocessing capabilities allows TigerSHARC processor to offer unrivaled DSP performance. At 600MHz clock rate, ADSP-TS201S offers industry's highest 16-bit fixed-point and 32-bit floating point performance. The ADSP-TS201S has 1024-point complex FFT time of 16.8 microseconds and provides 1500 MFLOPs per watt.
  • Static superscalar architecture which supports 1-, 8-, 16- and 32-bit fixed point as well as floating point data processing
  • High performance up to 600MHz, 1.67ns instruction rate DSP core
  • 24MB on-chip embedded DRAM internally organized in six banks with user-defined partitioning
  • Enhanced communications instruction set for wireless infrastructure applications allows for TigerSHARC processor to offer complete baseband processing
  • 14 channel, zero overhead DMA controller
  • Four internal 128-bit wide internal buses providing total memory bandwidth of 38.4Gbps
  • Software radio approach allows for adaption of single platform for multiple wireless telecommunication standards
  • Single instruction multiple-data (SIMD) operation supported by two computation blocks each with ALU, multiplier, shifter and 32-word register file
  • Assembly and C language programmability
 
Request Quote
 

Suggested Products